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K. Naresh Kumar is a passionate VLSI design and verification engineer with 16+ years of experience, including 13 years in academia and 3+ years in industry. He specializes in SystemVerilog, UVM, AMBA protocols (AXI, AHB, APB), and RISC-V IP/SoC verification, and is known for simplifying complex verification concepts through clear, practical teaching. Having trained several hundred learners, he continues to inspire and prepare engineers with strong industry-ready skills and a deep commitment to verification excellence.

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RISC-V

RISC-V SoC Verification: A Practical View from IP to Subsystem to Full Chip

Modern RISC-V SoC verification is fundamentally integration- and software-driven. Unlike  traditional SoCs, where peripherals are often treated as independent blocks, a RISC-...
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Verification

Why Formal Verification is Essential in Modern Hardware Design

In today’s hardware and software design, ensuring systems work correctly is more important than ever. Formal verification is a method that uses mathematics and logic to prov...
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Verification

Essential Role of Formal Verification in Hardware Design

In today’s hardware and software design, ensuring systems work correctly is more important than ever. Formal verification is a method that uses mathematics and logic to prov...
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