Avatar photo

author

Geetha brings over 8+ years of experience in teaching and training to ECE graduates. Her areas of interests are Front-end RTL Design and Design for Testability (DFT). Her passion for VLSI design is reflected in her blogs, where she breaks down complex concepts into simpler ones and provides practical insights for learners in the semiconductor industry.

View All Authors
Digital Electronics

Applications of an FSM with Output Toggle When Detecting Specific Patterns

In digital electronics, Finite State Machines (FSMs) form the backbone of most control oriented logic. From communication protocols, processors to embedded controllers, FSMs ...
Read More
DFT

SCAN COMPRESSION IN DESIGN FOR TESTABILITY

In Design for Testability (DFT), scan compression refers to the techniques used to reduce the test data volume and test time associated with scan-based testing of Integrated C...
Read More
DFT

DFT Golden Rules

The purpose of Design for Testing (DFT) in VLSI chips is to increase the accessibility of internal nodes. Controllability: the ability to establish a specific signal value at ...
Read More
Whatsapp