Introduction
As semiconductor innovation pushes the boundaries of performance and scalability, the industry
is shifting from monolithic system-on-chip (SoC) designs to chiplet-based architectures. This
modular approach allows designers to integrate specialized dies—known as chiplets—into a
single package. However, seamless communication between these chiplets demands a robust,
standardized interconnect. UCIe (Universal Chiplet Interconnect Express): an open industry
standard that enables high-bandwidth, low-latency die-to-die connectivity across heterogeneous
chiplets.
Why UCIe Matters
Traditional interconnects like PCIe and CXL are optimized for board-level communication.
UCIe, by contrast, is purpose-built for in-package die-to-die links, offering:
• Interoperability across vendors and foundries
• High data rates up to 64 GT/s per lane (UCIe 3.0)
• Modular scalability for AI(Artificial Intelligence), HPC(High Perfomance Computing), and consumer devices
• Power efficiency critical for dense multi-die systems
• Support for advanced packaging like 2.5D and 3D integration
Chiplet to Chiplet Communication:
Chiplet-to-chiplet communication refers to the methods and protocols used for data exchange
between individual chiplets within a multi-chip module (MCM) or advanced packaging system.
Instead of building a monolithic SoC (System on Chip), designers now use chiplet smaller,
modular dies that specialize in different functions (CPU, GPU, memory, I/O, etc. ) and connect
them efficiently.The Universal Chiplet Interconnect Express (UCIe) is designed to solve
one of the biggest challenges in modern chip design: how to efficiently connect chiplets
from different vendors, technologies, and process nodes inside a single package.
• UCIe defines a common physical and protocol layer for chiplets to talk to each other.
• Eliminates the need for custom interconnects between dies.
• Enables plug-and-play integration of chiplets from different sources.
Architecture Overview
1. Protocol Layer
• Supports multiple upper-layer protocols:
– PCIe
– CXL
– Custom protocols for specialized workloads
2. Die-to-Die Adapter Layer
• Link initialization and management
• Flow control and error handling
• Optional CRC and retry mechanisms
3. Physical Layer
• Supports both standard organic substrates and advanced silicon interposers
• Data rates:
– UCIe 1.0: up to 32 GT/s
– UCIe 3.0: up to 64 GT/s
• Lane scalability: from x4 to x64 configurations
Key Features by Version
| Version | Highlights |
| UCIe 1.0 | Foundational spec, PCIe/CXL support, 32 GT/s |
| UCIe 1.1 | Runtime health monitoring, multiprotocol support |
| UCIe 2.0 | 3D packaging, enhanced manageability |
| UCIe 3.0 | 64 GT/s, optimized for AI and HPC workloads |
Industry Adoption
UCIe is backed by a consortium of leading tech companies, including:
• Intel (founding contributor)
• AMD, Arm, TSMC, Samsung
• Google, Microsoft, Meta
• ASE, Qualcomm, NVIDIA
This broad support ensures that UCIe will become the de facto standard for chiplet interconnects
across diverse ecosystems.
Use Cases
• AI accelerators with modular compute and memory dies
• High-performance computing (HPC) with scalable bandwidth
• Consumer electronics with optimized power and cost
• Custom silicon for edge, automotive, and industrial applications
UCIe is a newer standard aimed at die-to-die (chiplet) communication within a single package,
enabling modular and scalable System-on-Chip (SoC) architectures. In contrast PCIe is a well-
established interface standard designed for board-level communication between a CPU and
external components such as GPUs, SSDs, and network cards.
PCIe vs UCIe – Major Differences
| No. | Aspect | PCIe (Peripheral Component Interconnect Express) | UCIe (Universal Chiplet Interconnect Express) |
|---|---|---|---|
| 1 | Scope of Use | Connects components across a motherboard/system (external communication). | Connects multiple dies/chiplets within a single package (internal communication). |
| 2 | Physical Layer | Uses SerDes lanes over PCB traces and connectors. | Uses short-reach interconnects on silicon interposers or advanced packaging. |
| 3 | Bandwidth Density | Moderate bandwidth (~1 Tbps/cm²). | Very high bandwidth density (~10 Tbps/mm²). |
| 4 | Latency | Relatively high (tens–hundreds of nanoseconds). | Ultra-low (a few nanoseconds). |
| 5 | Power Efficiency | Higher power (~10 pJ/bit). | Very low power (<1 pJ/bit). |
| 6 | Use Case | CPU ↔ GPU, SSD, NIC, FPGA (board-level). | CPU ↔ GPU, accelerator, memory chiplet (package-level). |
| 7 | Protocol Support | Uses PCIe protocol only. | Supports PCIe, CXL, or custom die-to-die protocols. |
Conclusion
UCIe is more than just a protocol—it’s a paradigm shift in how chips are designed, packaged, and scaled. By enabling plug-and-play interoperability across chiplets, UCIe unlocks new possibilities for performance, efficiency, and innovation in the semiconductor world.
