Simulation is one of the most important steps in the digital design flow. Before a design is synthesized, implemented, and finally converted into hardware, engineers need to verify that it behaves as expected.
Two commonly used simulation stages are RTL simulation and Netlist simulation. Both are important, but they operate at different levels of abstraction and are used for different purposes.
A simple way to remember the difference is
RTL simulation checks what the designer intended. Netlist simulation checks what synthesis actually produced.
Let’s understand the difference between the two.
What is RTL Simulation?
RTL stands for Register Transfer Level. RTL describes the design using hardware description languages such as Verilog, SystemVerilog, or VHDL.
At this stage, the design is represented using registers, combinational logic, state machines, counters, multiplexers, and other behavioral constructs.
For example:
always_ff @(posedge clk) begin
if (reset)
count <= 0;
else
count <= count + 1;
end
In RTL simulation, the simulator executes this description and checks whether the design behaves according to the specification.
The main objective is functional verification.
Engineers use RTL simulation to verify:
- Functional correctness
- Reset behavior
- State-machine transitions
- Data-path operations
- Control logic
- Interface protocols
- Corner cases
- Different operating scenarios
RTL simulation is generally fast and relatively easy to debug because the signals in the waveform have a direct relationship with the RTL source code.
For example, if a state machine moves from IDLE to EXECUTE unexpectedly, the designer can
usually trace the issue directly to the RTL logic.
What is Netlist Simulation?
Once RTL design is complete, it goes through synthesis. Synthesis converts the RTL into a gate-
level representation called a netlist.
Instead of high-level RTL constructs, the netlist contains actual logic elements such as:
- Flip-flops
- AND/OR gates
- Multiplexers
- Buffers
- Inverters
- Technology-specific standard cells
For example, a simple RTL expression such as:
assign y = (a & b) | c;
may be converted by synthesis into a combination of standard cells.
Netlist simulation runs this synthesized gate-level design through a simulator.
The purpose is to verify that the synthesized implementation still behaves correctly and, depending on the type of netlist simulation, to analyze the effects of timing delays.
RTL Simulation vs Netlist Simulation
| Feature | RTL Simulation | Netlist Simulation |
|---|---|---|
| Design level | RTL | Gate level |
| Main purpose | Functional verification | Gate-level/implementation verification |
| Synthesis required | No | Yes |
| Simulation speed | Faster | Slower |
| Debugging | Easier | More difficult |
| Logic representation | Behavioral/RTL constructs | Gates and standard cells |
| Timing | Usually abstract | Can include timing delays |
| Waveforms | Easier to understand | More detailed and complex |
| Typical stage | Before synthesis | After synthesis/implementation |
Why Is RTL Simulation Faster?
RTL is more abstract than a gate-level netlist.
Consider a simple operation:
assign y = (a & b) | (c & d);
At RTL, the simulator can evaluate the expression directly.
After synthesis, the same logic may be represented by multiple gates and standard cells. For a large design, the number of simulated objects can increase significantly.
As a result, netlist simulation is generally slower than RTL simulation, particularly when timing information is included.
This is one reason why large functional regressions are normally performed at the RTL level.
Debugging Differences:
Debugging is another major difference.
RTL simulation is much easier to debug because the signals usually have meaningful names and correspond directly to the designer’s source code.
In netlist simulation, the design may contain thousands or millions of internal nets and technology-specific cells. A simple RTL signal may have been optimized, renamed, or transformed during synthesis.
Therefore, finding the root cause of a failure at gate level can take considerably more effort.
For this reason, engineers generally try to identify and fix functional bugs during RTL simulation rather than waiting for netlist simulation.
Why Do We Need Netlist Simulation?
If RTL simulation already passes, why do we need to simulate the netlist?
The reason is that RTL and synthesized hardware are not represented in the same way.
Synthesis transforms the RTL into an implementation using the available technology cells. Logic can be optimized, transformed, or mapped into different structures.
Netlist simulation provides an additional check after this transformation.
It can be useful for checking:
- Gate-level functional behavior
- Reset and initialization behavior
- X propagation
- Synthesis-related issues
- Clock and reset implementation
- Timing behavior when delays are annotated
However, netlist simulation should not be considered a replacement for RTL verification. It is an additional step that provides confidence in the implementation.
When Should We Use RTL and Netlist Simulation?
RTL simulation should be used extensively during design and verification because it is fast and easy to debug.
It is especially useful when developing new blocks, debugging functional problems, and running large regression suites.
Netlist simulation is generally performed after synthesis or implementation, depending on the project requirements.
Conclusion:
RTL simulation and netlist simulation are both important parts of the digital design verification process, but they serve different purposes.
RTL simulation focuses mainly on functional correctness. It is faster, easier to debug, and is therefore the primary method used for verifying the design during development.
Netlist simulation works at the gate level and provides additional confidence after synthesis. When timing information is included, it can also help verify the behavior of the design with modeled cell and interconnect delays.
