Understanding the AMBA CHI Protocol: A Technical Overview

Modern high-performance SoCs rely on cache coherency to maintain consistent memory views across multiple CPUs, accelerators, and I/O devices. ARM’s AMBA CHI (CoherentHub Interface) is one of the most scalable and advanced on-chip interconnect protocols designed for multi-core, multi-cluster systems.

Introduced for ARM’s CCN (CoreLink Cache Coherent Network) and CMN (CoreLink
Mesh Network) families, CHI provides:

• High bandwidth and ultra-low latency interconnect
• Full cache coherency across clusters
• Support for hundreds of outstanding transactions
• Packet-based, fully decoupled channel architecture
• A highly scalable mesh/NoC-ready protocol 

This blog dives into CHI’s architecture, message types, ordering rules, credit system, and coherency mechanisms.

1. Why CHI Was Introduced

ARM previously used ACE/ACE-Lite, based on AXI. But ACE had limitations:

CHI enables large-scale coherent SoCs with clusters of CPUs, GPUs, NPUs, DSPs, and I/O
coherent units.

2. CHI Architecture Overview

CHI uses three fully independent, pipelined channels:

1. Request Channel (REQ)
   Carrying commands like ReadShared, ReadUnique, WriteBack, etc
2. Response Channel (RSP)Data Channel (DAT)
   Returns acknowledgements, snoop responses, and completion messages.
3. Data Channel (DAT)
   Transfers data beats for reads, writes, snoop responses, linefills, etc.

Each channel transmits packets broken into flits (flow control units).The protocol avoids fixed wiring widths and enables NoC-optimised routing.

3. CHI Message Types

CHI is structured around message classes, including:

3.1 Request Messages

• ReadShared
• ReadUnique
• CleanUnique
• WriteBackFull
• WriteBackPartial
• Evict
• MakeUnique
• PrefetchTgt
  (And many more)

Requests are always sent towards the home node (directory).

3.2 Snoop Messages

Directed from the Home node → Peer caches:

• SnpShared
• SnpUnique
• SnpClean
• SnpOnce
• SnpFwd

3.3 Response Messages

Sent from Home/Slave → Requester or Snoop Target → Home:

• RspCompAck
• RspSnpResp
• RspError
• RspData
• RspReadReceipt

Responses ensure ordering and indicate whether snoop participation is required.

3.4 Data Messages

Carry cachelines (usually 64B) as:

• DataResp
• DataSnpResp
• DataWriteBack
• DataShared
• DataClean

CHI decouples data from requests/responses, enabling higher concurrency.

4. CHI Coherency Model

CHI implements a directory-based version of MOESI:

• Modified (M)
  • The cache line is dirty (different from main memory).
  • Only this cache has the updated copy.
  • Before another processor can read it, the data must be written back to memory.
    
• Owned (O)
  • The cache line is dirty but shared.
  • One cache is the “owner” and responsible for eventually writing the data back
    to memory.
  • Other caches may hold a shared copy, but they rely on the owner for
    correctness.
• Exclusive (E)
  • The cache line is clean (matches main memory).
  • Only one cache has this copy.
  • If modified, it transitions to the Modified state without notifying others.
• Shared (S)
  • The cache line is clean and may exist in multiple caches.
  • Since it matches memory, no single cache is responsible for writing it back.
• Invalid (I)
  • The cache line is not valid (no data present).
  • Accessing it triggers a fetch from memory or another cache.

The directory tracks sharers/owner and determines snoop sequencing.

Key advantages:

• Minimal unnecessary snoops
• Optimal bandwidth usage
• Reduced latency due to targeted snoops
• CHI follows a loosely-ordered philosophy with some rules:to 100+ caching agents

5. CHI Ordering Model 

CHI follows a loosely-ordered philosophy with some rules:

Global Memory Ordering:

• Within a single master, ordering must be preserved for the same address.
• Between different addresses, CHI allows out-of-order completion. 

Request → Response → Data Ordering:

Each channel is independent, meaning:

• Request can be acknowledged early (RspReadReceipt)
• Data can flow before some responses
• Completion order can vary for performance

Ordering is maintained using:

• Transaction ID (TID)
• Source/Destination IDs
• Tag fields
• QoS/priority fields

6. Flow Control and Credits System

CHI uses a credit-based flow control mechanism:

• Each endpoint advertises available credits for REQ/RSP/DAT channels.
• Sender decreases credit when sending a packet.
• Receiver returns credits once it processes flits.

Benefits:

• No risk of buffer overflow
• Fully pipelined, high-frequency NoC operation
• Efficient arbitration and congestion handling 

7. Typical CHI Transaction Sequence

Let’s examine a ReadUnique transaction: 

1. Request Node → Home Node
   Sends a ReadUnique REQ.
2. Home Node → Remote Sharers
   Issues SnpUnique snoops.
   
3. Sharers → Home Node
   Respond with SnpResp / Data.
4. Shared (S)
   • Sends final CompAck
   • Sends data (from memory or another cache) 
5. Requester
   Updates its local cacheline to Modified state.

This illustrates how CHI ensures all peers observe coherent state transitions.  

8. CHI in Modern Systems 

CHI is widely used in: 

• ARM Neoverse platforms
• High-performance mobile SoCs
• Automotive ADAS processors
• Heterogeneous compute fabrics (CPU + GPU + NPU)
• Server-class mesh networks 

Successor variants like CHI-B, CHI-C, and CHI-E extend packet flexibility and memory semantics for next-generation platforms. 

9. Verification of CHI Protocol 

Verification challenges include:

• Complex message-based architecture
• Hundreds of transaction permutations
• Large-scale multi-agent coherency interactions
• Snoop fanouts and directory state transitions
• Reorderings across three independent channels  

Typical UVM CHI VIP environments use:

• Per-channel agents (REQ/RSP/DAT)
• Scoreboards tracking Home–Requester–Snoop coherence
• Functional coverage of:
  • • Message types
    • State transitions
    • Outstanding transactions
    • Credit flow events 

10. Conclusion

AMBA CHI is a sophisticated, scalable, and high-performance coherence protocol tailored for large heterogeneous SoCs. Its packet-based, directory-driven design provides:

• Lower latency
• Larger system scalability
• Better throughput
• Decoupled traffic channels
• Efficient snoop control

As systems continue to scale beyond hundreds of cores, CHI forms the backbone of ARM’s coherent interconnect architecture.