In an embedded system design, efficiency and real-time responsiveness are king.
Whether it is a microcontroller-driven sensor system, a Robotic Controller or IOT, how we handle external events has a significant impact on the system’s performance.
There are two classic approaches: Polling and ISRs
The Polling Paradigm: “They quickly hit limits in a complex system”
Polling means the CPU repeatedly checks the status of a peripheral or input pin in a loop to see if an event has occurred.
C-code snippet
In the above code, the “while” loop has created an infinite loop- meaning the code inside it runs continuously forever, meaning the processor never rests. It keeps looping rapidly.
The function “GPIO_PIN_READ” reads the logic level of the specified GPIO pin connected to the button.
- If the pin reads 1, it means the button is not pressed
- If the pin reads 0, it means the button is pressed
Why is this inefficient?
- The CPU is 100% busy, even if the button is never pressed
- This wastes power and processing time of the CPU
- CPU continuously spin, checking the input pin – doing nothing else useful meanwhile
Microcontrollers commonly using polling
- AVR (Arduino Uno)family
- PIC16F84
- PIC12F675
- 8051-based MCUs
ISR (Interrupt Service Request): An alternative
- The CPU doesn’t constantly check the button
- Rather, there is a hardware called an Interrupt Controller inside the microcontroller, which notifies the CPU only when there is an event on the peripheral.
- The peripheral hardware detects an event (say HIGH->LOW) and will set a flag in its Interrupt status register. This, in turn, sends an interrupt signal to the Interrupt Controller.
- The Interrupt Controller notifies the CPU regarding the event by triggering an interrupt request line.
- When the CPU receives the interrupt, it pauses its current execution and jumps to a specific address in the RAM (The Interrupt Vector Table).
- This address points to the Interrupt Service Routine that has the functions defined.
- The flag in the Interrupt status register is cleared, and the CPU returns to the main program where it was left off.
- This approach doesn’t need continuous checking, hence CPU cycles are not wasted.
Example of Interrupt Controllers based on the Processor
- ARM Cortex-M has NVIC (Nested Vectored Interrupt Controller)
- RISC-V has PLIC (Platform-Level Interrupt Controller) or CLINT(Core Level Interrupter)
C code snippet
The above code is the interrupt handler routine, which is invoked by the processor after an interrupt has occurred.
Why is this efficient?
- The CPU is only interrupted when an event occurs
- The CPU load is less
